Is there any real benefit in using 3 phase shunt resistors vs 2 other than high current sampling mode? I see in code that in different vectors it use different shunts pair but does it help?

In practice it helps quite a lot, as it enables sampling the current far away from the switching cycles even at high speed. This can be noted on HW4 where a commanded constant current will give a non-linear acceleration: it will be linear to around 60% of full speed, then it will decrease for a bit up to around 80 % and then it will increase from 80% to 100%. If you give full throttle and pay attention to this, the effect is very obvious. I spent a lot of time trying to work around this, but it is not easy as it depends on many things and behaves differently on different motors and voltages. The current simply becomes noisy and gets aliasing at certain motor phase angles at high speed when using two shunts. Analog filtering is also not possible in the same way as with three shunts as the rise time has to be very fast at high modulation for two shunts to work. The VESC6 has a smooth linear acceleration from 0 to full speed, and this is mostly because it uses three shunts.

Two phase shunts are slightly better than two low side shunts, but three shunts are still the best. I would prefer three low side shunts over two phase shunts in general, if that is a choise to be taken in a design (e.g. when making hardware that supports 100+ volts).

it enables sampling the current far away from the switching cycles even at high speed

Are you sure? A'm not talking about 2 lowside shunts vs 3 phase shuts but 2 phase vs 3 phase shunts. How it can make difference when one current is calculated anyway and I assume that they are sampled in same time regardless of shunts count. Are you taking 2 largest values from 3 measured to have less quantization error or am I missing something?

This can be noted on HW4 where a commanded constant current will give a non-linear acceleration

HW4 - no phase shunts

The current simply becomes noisy and gets aliasing at certain motor phase angles at high speed when using two shunts. Analog filtering is also not possible in the same way as with three shunts as the rise time has to be very fast at high modulation for two shunts to work

This sound like problem caused by using low side shunts.

Current sampling is one of the topics I have spent the most time on, so I'm quite sure about the statements. It is not easy to explain though, as you have to understand how the modulation works under all conditions. BLDC is also very different from FOC, and for both BLDC and FOC there are different ways to do the modulation that affect current sampling.

In most cases it comes back to one thing when using only two shunts: sampling when the time between the switching edges on one particular phase is short. If currents are sampled at the same time during high modulation and you look at the state of each phase individually, they will vary between being off for a short time and being on for a short time during one electrical revolution, meaning that if you pick a fixed sample time it will always slide past switching edges that affect the measurement in one particular phase. It is when the switching edges come close to the sample time that causes the issue, and you want to stay away from it when sampling that phase. One common way to deal with that is sample in a zero vector and pick the sample point in the middle, and limiting the modulation to e.g. 95% so that the switching edges never cross the sample point. Even when using phase shunts you can't have too slow filters as the switching edge will get really close to the sample point and you want the filter to settle in time for taking the sample.

With three shunts you can always find two phases that are far away from a switching edge when taking a sample if the sampling point is fixed, but with two shunts that cannot be done regardless of which sample time you pick, even with phase shunts. One thing that can be done with phase shunts and FOC with SVM for example is sampling in both V0 and V7 of the SVM cycle and picking the samples furthest away from any switching edge, but the problem when doing that is that control is done with current measured at different times and thus positions that can be quite far apart if the switching frequency is low compared to the motor speed. I spent some time experimenting with that, but the performance was simply not that good.

Again, If I have to choose between two phase shunts and three low side shunts, I would pick three low side shunts for sure.

The three ADCs actually are configured to sample the currents and voltages at the same time, but it would probably work with just one ADC sampling them consecutively if it is fast enough. Sampling all currents and voltages at exactly the same time is always better though if it is possible.

On FOC does PWM freq have any impact on current sensing? Does current sensing represent any sort of bottleneck on max ERPM? When selecting current sense ICs what do you find has the largest impact on performance?

So what is the time window for current limiting? I am trying to work out what peak currents would be with different inductance motors as it can vary a lot.

How long does it take before the VESC will try to limit the current? Is it the period of the PWM or shorter?

Does phase shunt mean inline shunt?
Which is it better low side shunt or inline shunt?
I have developed vesc 6 derivative using the DRV8323RS chipset.
The DRV8323RS have 3 amplifier for low side shunt resistor and all is same in power stage.
But It have problem in current mode control. So I have tried test changing the parameters.
The problem is cleared by "v0 and v7 sample" to off.

Regardless of the 3 shunts, is v0 and v7 just options for the phase shunt?

In practice it helps quite a lot, as it enables sampling the current far away from the switching cycles even at high speed. This can be noted on HW4 where a commanded constant current will give a non-linear acceleration: it will be linear to around 60% of full speed, then it will decrease for a bit up to around 80 % and then it will increase from 80% to 100%. If you give full throttle and pay attention to this, the effect is very obvious. I spent a lot of time trying to work around this, but it is not easy as it depends on many things and behaves differently on different motors and voltages. The current simply becomes noisy and gets aliasing at certain motor phase angles at high speed when using two shunts. Analog filtering is also not possible in the same way as with three shunts as the rise time has to be very fast at high modulation for two shunts to work. The VESC6 has a smooth linear acceleration from 0 to full speed, and this is mostly because it uses three shunts.

Two phase shunts are slightly better than two low side shunts, but three shunts are still the best. I would prefer three low side shunts over two phase shunts in general, if that is a choise to be taken in a design (e.g. when making hardware that supports 100+ volts).

Are you sure? A'm not talking about 2 lowside shunts vs 3 phase shuts but 2 phase vs 3 phase shunts. How it can make difference when one current is calculated anyway and I assume that they are sampled in same time regardless of shunts count. Are you taking 2 largest values from 3 measured to have less quantization error or am I missing something?

HW4 - no phase shunts

This sound like problem caused by using low side shunts.

Thanks for response and correct me if I'm wrong.

Current sampling is one of the topics I have spent the most time on, so I'm quite sure about the statements. It is not easy to explain though, as you have to understand how the modulation works under all conditions. BLDC is also very different from FOC, and for both BLDC and FOC there are different ways to do the modulation that affect current sampling.

In most cases it comes back to one thing when using only two shunts: sampling when the time between the switching edges on one particular phase is short. If currents are sampled at the same time during high modulation and you look at the state of each phase individually, they will vary between being off for a short time and being on for a short time during one electrical revolution, meaning that if you pick a fixed sample time it will always slide past switching edges that affect the measurement in one particular phase. It is when the switching edges come close to the sample time that causes the issue, and you want to stay away from it when sampling that phase. One common way to deal with that is sample in a zero vector and pick the sample point in the middle, and limiting the modulation to e.g. 95% so that the switching edges never cross the sample point. Even when using phase shunts you can't have too slow filters as the switching edge will get really close to the sample point and you want the filter to settle in time for taking the sample.

With three shunts you can always find two phases that are far away from a switching edge when taking a sample if the sampling point is fixed, but with two shunts that cannot be done regardless of which sample time you pick, even with phase shunts. One thing that can be done with phase shunts and FOC with SVM for example is sampling in both V0 and V7 of the SVM cycle and picking the samples furthest away from any switching edge, but the problem when doing that is that control is done with current measured at different times and thus positions that can be quite far apart if the switching frequency is low compared to the motor speed. I spent some time experimenting with that, but the performance was simply not that good.

Again, If I have to choose between two phase shunts and three low side shunts, I would pick three low side shunts for sure.

Now I get it. I got confused by fact that MCU got 3 ADCs. Is there use of them or it can work fine with just one ADC?

The three ADCs actually are configured to sample the currents and voltages at the same time, but it would probably work with just one ADC sampling them consecutively if it is fast enough. Sampling all currents and voltages at exactly the same time is always better though if it is possible.

I'm quite interested in current sensing as well.

On FOC does PWM freq have any impact on current sensing? Does current sensing represent any sort of bottleneck on max ERPM? When selecting current sense ICs what do you find has the largest impact on performance?

So what is the time window for current limiting? I am trying to work out what peak currents would be with different inductance motors as it can vary a lot.

How long does it take before the VESC will try to limit the current? Is it the period of the PWM or shorter?

Does phase shunt mean inline shunt?

Which is it better low side shunt or inline shunt?

I have developed vesc 6 derivative using the DRV8323RS chipset.

The DRV8323RS have 3 amplifier for low side shunt resistor and all is same in power stage.

But It have problem in current mode control. So I have tried test changing the parameters.

The problem is cleared by "v0 and v7 sample" to off.

Regardless of the 3 shunts, is v0 and v7 just options for the phase shunt?

Yeah v0 and v7 sampling is for phase shunts only.

Does the phase shunt means resistor wired to motor wire and middle tap of high side MOSFET and low side MOSFET?

It is called generally inline mode shunt.

By the way, Which is it better low side 3 shunts without v0_v7 sampling or 3 phase shunts with v0_v7 sampling?

Yes between centre tap of fets and motor wire.

phase shunts are better as you can sample them for both high and low side currents.

As by said you and Benjamin,

3 phase shunts > 3 low side shunts > 2 phase shunts > 2 low side shunts,

What do you think about my result?

Yeah that is correct. I will probably be using 3 low side shunts for my 100v+ hardware.