I'm building a beefed-up version of the VESC.
When I measure a low-side gate, I see this:
So... When the low-side FET turns on, after a while the turn-on is so fast that through the output capacitance of the FET the gate turns completely off again. Not quite a miller plateau.
This happens almost 3 times in 100ns, so at about 30Mhz. Now I could increase the gate resistance to make the turn-on slower, but this also gives my gate driver less authority to keep the gate at the "wanted" voltage.
My gate driver claims "4A", and I now have 4.7 Ohm gate resistors. So with the gate driver being close to 10V already, with a negative gate voltage we should be seeing > 2A through the gate resistor. Oh. I have two parallel FETs nowadays..... They have separate gate resistors.
The probes are 1:10 so when the scope says 500mV/div it really means 5V/div. As you can see I'm running at 24V right now. (at around trigger-500ns you can see that the highside fet releases this phase so the voltage rises to 24.6V)