Hello, first of all, thanks for the brilliant work!
I started with an FSESC 6.6 about 4 years ago. Using an Alien X8318 100KV – 42 pole on a bike. The wires between ESC and motor are about 40 cm long. Apart from some minor issues, everything went well. After a while, it started to get sporadic resets with immediate stoping motor (free wheeling bike). These resets got more frequent and end up to appear every few seconds. To narrow the source of the resets, I tried to change the control parameters, flashed newer SW, etc. And it often seemed that the resets disappeared, but after a while I always ended up in resets every few seconds. As there was always a possibility that it might be a hardware problem, I kept up with testing. The problem was, that on the bench, I was not able to reproduce the frequent resets. And when the resets happened I had no chance to protocol them. So now I ended up with trying a new/different hardware - FSESC 75100- with FW 6.02 for 75100 and 75300 and now I get the resets all the time. So the analysis is:
It makes no(meassurable) difference if the wires between the motor and ESC are mounted separated or parallel (influencing each other).
It happens in FOC and BLDC, with current, speed or duty-control at any ERPM. Changing the control-parameters make no difference.
For frequent resets the motor current should be >20A (50A max.)
There are no fault messages, and the protocol does not show any abnormality before the resets, apart from less timestamps in 75-100
The (external) 3.3 V is very stable, so most likely it is no brown-out.
As there are no relevant fault messages in the protocol, I guess that the most likely reason for the resets is a WD-reset, as the behavior of the reset is very similar each time.
Changing the motor to a ‚normal‘ 12-pole motor, there are no resets at all
As the motor runs for quite a few seconds in the same ‚static‘ mode ( flat paved road) before reseting, and as it runs perfect with 12 -pole motors my guess is that the ‚wind-up‘ of the SW happens somewhere in the back-reading of the EMF-signals from the motor. Before the path gets separated for FOC and BLDC.
Already knowing, that there were some issues with these multipole motors, I went through the boards and found some discussions that there are some minor issues about these motors together with the VESCs, but not about resets.
Watch for the time stamps just before the resets, there are less entries in 75-100/BLDC! This also points to WD-resets. As for 6.6/FOC, this behavior before the resets is less (not?) present.
here you find the logs:
https://c.gmx.net/@325219879995048785/z6MXTR5ySPGiewSy6AhkcQ
Protocol with BLDC-mode and 75100 on BLE, so the resets can be seen at the missing time stamps. ( BLDC -mode), FW6.02.
2023-06-03_10-54-39 frequent resets, less timestamps before reset
and FSESC 6.6 (a second one, as with the first one, the ADC1 got unusable with one of the resets, showing always around 2,6V) with FOC-mode. FW6.02
2023-06-23_18-28-04 Line 3687
2023-06-23_18-39-59 Line 4126, 14963, 15677
Hope that you find the reason for that behavior, as the bike is not of big use with the actual behavior, and the resets are a continouse thread for fried HW, as already happened.