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Uploading firmware bricked VESC

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daveshorts
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Last seen: 1 year 11 months ago
Joined: 2018-02-04 13:20
Posts: 2
Uploading firmware bricked VESC

I am trying to work out what dumb thing I have done.

I bought an assembled and working VESC. I wanted to create a custom firmware so followed the instructions with the example on vedder.se, and uploaded it with the STlink

I first used the default ubuntu 16.04 toolchain, but have since upgraded using the instructions here

http://vesc-project.com/node/310

I have since gone back to using the vanilla version from the github repository.

If I upload the firmware using make upload it seems to upload ok

If I upload the bootloader it seems to upload but hangs on the

** Resetting Target **   stage

If I run the openocd command with -d3 to get more info it seems to hang on:

Debug: 6432 4588 command.c:145 script_debug(): command - init ocd_init

The vesc sits there flashing its red led twice if plugged into the STlink or not at all if powered from a battery.

If I connect to bldc-tool  (again from github) it claims I have an old version of the firmware and that I should upload a newer version

I have changed the hardware version to 4.12 (my board) in conf_general.c

I can't see any error messages

 

 

Does anyone have any idea what is going on? As I have never used STM32s before and I am feeling somewhat blind in my attempts to fix it.

   thanks

 

Results of make upload in firmware

openocd -f board/stm32f4discovery.cfg -c "reset_config trst_only combined" -c "program build/BLDC_4_ChibiOS.elf verify reset exit" # For openocd 0.9
Open On-Chip Debugger 0.9.0 (2015-09-02-10:42)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter speed: 2000 kHz
adapter_nsrst_delay: 100
none separate
srst_only separate srst_nogate srst_open_drain connect_deassert_srst
trst_only combined trst_push_pull
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : clock speed 1800 kHz
Info : STLINK v2 JTAG v21 API v2 SWIM v4 VID 0x0483 PID 0x3748
Info : using stlink api v2
Info : Target voltage: 3.243243
Info : stm32f4x.cpu: hardware has 6 breakpoints, 4 watchpoints
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x0800c000 msp: 0x20000800
** Programming Started **
auto erase enabled
Info : device id = 0x10076413
Info : flash size = 1024kbytes
Info : Padding image section 0 with 48704 bytes
Info : Padding image section 1 with 4 bytes
target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x20000042 msp: 0x20000800
wrote 262144 bytes from file build/BLDC_4_ChibiOS.elf in 8.767796s (29.198 KiB/s)
** Programming Finished **
** Verify Started **
target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20000800
target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20000800
target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20000800
verified 151000 bytes in 1.393879s (105.792 KiB/s)
** Verified OK **
** Resetting Target **
shutdown command invoked

Results of make upload bootloader

#qstlink2 --cli --erase --write build/BLDC_4_Bootloader.bin
openocd -f interface/stlink-v2.cfg -c "set WORKAREASIZE 0x2000" -f target/stm32f4x.cfg -c "program build/BLDC_4_Bootloader.elf verify reset"
Open On-Chip Debugger 0.9.0 (2015-09-02-10:42)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
0x2000
Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'.
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter speed: 2000 kHz
adapter_nsrst_delay: 100
none separate
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : clock speed 1800 kHz
Info : STLINK v2 JTAG v21 API v2 SWIM v4 VID 0x0483 PID 0x3748
Info : using stlink api v2
Info : Target voltage: 3.243243
Info : stm32f4x.cpu: hardware has 6 breakpoints, 4 watchpoints
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x0800c000 msp: 0x20000800
** Programming Started **
auto erase enabled
Info : device id = 0x10076413
Info : flash size = 1024kbytes
target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x20000042 msp: 0x20000800
wrote 131072 bytes from file build/BLDC_4_Bootloader.elf in 4.266656s (30.000 KiB/s)
** Programming Finished **
** Verify Started **
target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20000800
verified 4288 bytes in 0.071080s (58.912 KiB/s)
** Verified OK **
** Resetting Target **
^CMakefile:237: recipe for target 'upload' failed
make: *** [upload] Interrupt

 

 

 

daveshorts
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Last seen: 1 year 11 months ago
Joined: 2018-02-04 13:20
Posts: 2

Ok the problem was that I was usng bldc_tool not vesc_tool, and the firmware is in the same repository, so following the instructions

http://vedder.se/2015/01/vesc-open-source-esc/

will work except bldc_tool is not compatible with the more modern firmware and complains of 'old firmware'. And vesc-project is not mentioned on the vedder.se page that is top of the google results for VESC.

That was 2 days I will never see again...

 Lovely piece of kit and software. If, for the sake of the non-psychic numpties like me, a link made it onto the top of th vedder.se page that would probably be appreciated by many others.

Thanks

Jorgmes
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Last seen: 7 months 1 week ago
Joined: 2019-06-17 12:31
Posts: 1

Uploading firmware bricked VESC isthe real develpment with the working ideas. All the ideasare true to us and people will relate it with best resume writing companies 2019 tasks. I am working on the concepts of real world.

yuvikal
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Last seen: 1 month 1 week ago
VESC Free
Joined: 2019-12-12 21:24
Posts: 3

Hi guys.

I was stupid enough to updating my FW to Unity when i have the VESC 4.12 HW. 

now its bricked.

Is there any way to rewrite to whole thing again whe i cant connect to it?

 

henry10210
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Last seen: 3 days 22 hours ago
VESC Free
Joined: 2019-12-16 18:06
Posts: 7

Hi Dave, I am a newbie too (although I am a FW engineer and comfortable with the ST HW and toolchain).  I haven't received the battery adapter for the VESC6 MK3 I bought from Trampa Boards, so I can't answer this question for myself yet, so I am curious: why didn't you just try updating the FW from the VESC-tool in the first place?  I know about the "make upload", but if you have a VESC with a functional bootloader, wouldn't this be the safer way to go?  I would have guessed that the SWD route is necessary if you do NOT even have a bootloader running.

BTW, since you say you modified the FW, do you by chance know the exact STM32F40x part?  I prefer SEGGER J-Link over ST-Link, and the precise part number is required for JLinkGDBServer.  Also helpful in looking up the pin assignments from the datasheet, but mayby Benjamin didn't specify because all STM32F40x are the same (guessing here)?  Where did you buy your VESC at?  I am actually kicking myself for having spent $1000 for MK3 since that schematic is not even available on this website.  I thought I was buying the VESC6+ but it is apparently a new product, and its code does not yet seem to be available in the bldc repo (please correct me if I am wrong).